High performance network hardware for Cluster computing
2008.03.31
(1)Maestro Project(1997-2002)
The cluster computing has become very popular in the world, which uses commodity components and achieves good cost/performance ratio for parallel computing. However, it is very hard for the conventional cluster computers to extract its potential performance due to its large overhead hided in the network hardware. Considering the cluster’s characteristics computer as an independent system, the optimization of communication is available.Read More
Maestro project proposed Network Burst and Pipelined transfer as the optimization technique oriented to cluster’s inter-connection network. The Network Burst divides a message into a small data chunk (called packet) and sends it in burst as much packet at a transfer opportunity. On the other hand, the Pipelined transfer propagates the packets to the devices in the network one after another. These techniques has been implemented on an FPGA as Maestro Link Controller with the Maestro Link Protocol that implements the two techniques above. According to the experimental evaluation with MLC, two techniques proposed above was effective for the optimization of inter-cluster communication.
Network interface of Maestro Cluster Network (64bit PCI@66MHz, IEEE1394 200Mbps PHY, PowerPC603e, 64MB EDO DRAM are embeded
8port Switch Box of Maestro Cluster Network (64bit PCI@66MHz, IEEE1394 200Mbps PHY, PowerPC603e, 64MB EDO DRAM are embeded)
Research articles in Journals and Magazines
Koichi Wada, Shinichi Yamagiwa, Munehiro Fukuda. High Performance Network of PC Cluster Maestro, Cluster Computing, 33--42, (2002-01-01), DOI:10.1023/a:1012788521068
S. Yamagiwa, K. Wada. Design and implementation of message passing library on Maestro network, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233), , (2001-08-26), DOI:10.1109/pacrim.2001.953529
S. Yamagiwa, M. Fukuda, K. Wada. Design and performance of Maestro cluster network, Proceedings IEEE International Conference on Cluster Computing. CLUSTER 2000, , (2000-11-28), DOI:10.1109/clustr.2000.888990
P. Kulkasem, S. Yamagiwa, N. Ito, N. Yonezawa, K. Wada. Design and implementation of message passing library for PC cluster Maestro, 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368), , (1999-08-22), DOI:10.1109/pacrim.1999.799608
Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, Koichi Wada. Maestro-link: A high performance interconnect for PC cluster, FPL 1998: Field-Programmable Logic and Applications From FPGAs to Computing Paradigm, 421--425, (1998-09-01), DOI:10.1007/bfb0055273
(2)Maestro2 Project(2002-
To improve the optimization techniques at Maestro project, Maestro2 project proposed continuous network burst transfer and out-of-order switching mechanism. The continuous network burst transfer was devised the Network Burst technique to keep longer burst transfer at a transfer opportunity. On the other hand, the out-of-order switching mechanism implemented a concurrent message transfer with a shred bus on the switchbox. In addition, Maestro2 Cluster Network has been implemented with MLX MLX(Maestro Link Protocol dupleX), and was evaluated with several communication experiment. The communication is made by a special communication software called MMP. According to the evaluations, the continuous network burst transfer and the out-of-order switching were effective to improve the intercluster communication.
Network interface of Maestro2 Cluster Network (64bit PCI@66MHz, LVDS 600Mbps PHY, PowerPC603e, 64MB SDRAM are embeded
8port Switch Box of Maestro2 Cluster Network (64bit PCI@66MHz, LVDS 600Mbps PHY, PowerPC603e, 64MB SDRAM are embeded)
Research articles in Journals and Magazines
Koichi Wada, Shinichi Yamagiwa, Munehiro Fukuda. High Performance Network of PC Cluster Maestro, Cluster Computing, 33--42, (2002-01-01), DOI:10.1023/a:1012788521068
S. Yamagiwa, K. Wada. Design and implementation of message passing library on Maestro network, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233), , (2001-08-26), DOI:10.1109/pacrim.2001.953529
S. Yamagiwa, M. Fukuda, K. Wada. Design and performance of Maestro cluster network, Proceedings IEEE International Conference on Cluster Computing. CLUSTER 2000, , (2000-11-28), DOI:10.1109/clustr.2000.888990
P. Kulkasem, S. Yamagiwa, N. Ito, N. Yonezawa, K. Wada. Design and implementation of message passing library for PC cluster Maestro, 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368), , (1999-08-22), DOI:10.1109/pacrim.1999.799608
Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, Koichi Wada. Maestro-link: A high performance interconnect for PC cluster, FPL 1998: Field-Programmable Logic and Applications From FPGAs to Computing Paradigm, 421--425, (1998-09-01), DOI:10.1007/bfb0055273
Prizes
Best Paper Award (CLUSTER2000) (Shinichi Yamagiwa, Munehiro Fukuda and Koichi Wada, “Design and Performance of Maestro Cluster Network,” Proceedings of IEEE International Conference on Cluster Computing (CLUSTER2000), IEEE, pp. 35-44, November 2000.).